This invention relates to bubble memories and their methods of fabrication. Over the last several years, much effort has been put into improving bubble memory fabrication processes in order to increase chip yield. One of the known factors that reduce chip yield is the existence of "steps" in the permalloy patterns as they cross over the various control conductors in the memory. Basically, the permalloy patterns provide bubble propagation paths in the memory, whereas the control conductors provide means for generating bubbles, transferring bubbles from one propagation path to another, and replicating bubbles. To implement these functions, the permalloy patterns are required to cross over the control conductors. However, it is well known that a step in the permalloy as it crosses over the conductor edge introduces a discontinuity in the magnetization of the permalloy. And the discontinuity sets up a barrier to bubble propagation. This in turn degrades the operating margins for the rotating and bias magnetic fields, and thus reduces chip yield.
To overcome this problem, various so called planar processes have been proposed. See for example, an article by J. P. Reekstin and R. Kowalchuck in the IEEE Transactions on Magnetism, Volume 9, page 485 (1973). See also, an article by D. K. Rose, IEEE Transactions on Magnetism, Volume 12, page 618, (1976). None of these proposed processes however, have been utilized to fabricate large capacity chips partly because they are too complicated to obtain good process yields.
Further, a "resist lift-off" step that is used in a planar process, is undesirable because it forms edge contours that are basically unreproducable. Prior to the lift-off step, the control electrodes are formed by patterning a layer of resist on an aluminous layer. Then the aluminous layer is patterned by either chemical etching or ion-milling. Subsequently, an insulating layer is formed over both the resist and the spaces lying therebetween. Then the "lift-off" step is performed to lift-off both the resist and the insulating material lying on top of the resist.
Ideally, the insulating material that remains in the regions between the conductors is of the same thickness as the conductors. And thus, no step occurs at the junction between the two. One problem however, is that during the lift-off step the insulating material that overlies the conductor cracks as the resist is being lifted off. Thus, a jagged unreproducable edge occurs at the junction between the conductors and the insulating material that remains after lift-off. This edge has a random shape that includes both peaks and valleys. And they in turn adversely affect bubble propagation and chip yield.
Further, the lift-off step can randomly cause pinhole shorts to occur at the junction between the conductors and the insulating material. These pinholes may be due to the cracking of the insulating material during lift-off as described above. But in addition, if the conductors are formed by chemical etching, the pinholes will be increased by undercutting of the resist. This undercutting results in a void in the undercut regions as the insulating region is formed on top of the resist and the areas therebetween. Then after lift-off, a gap exists between the conductors and the insulating material that remains.
Accordingly, it is one object of the invention to provide an improved method of fabricating magnetic bubble memories.
Another object of the invention is to provide a method of fabricating bubble memories having no step in the permalloy patterns as they cross the underlying conductors without using resist lift-off techniques.
Still another object of the invention is to provide an improved magnetic bubble memory by means of a novel fabrication process.